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Project Acronym TAMES-2
Title Testability of Analog Macrocells Embedded into System-on-Chip
Start date 01-March-2002
End date 31-July-2004
Programme IST

TAMES-2 addresses the problem of industrial testability of mixed signal interface macrocells containing data converters embedded in SoC. To focus on the main industrial requirements, e.g. improving the test quality while reducing test costs, a reusable DfT methodology will be defined, by introducing the key concepts of test reuse at SoC, architectural and circuit level. Innovative DfT techniques will be implemented in two IP blocks that have complementary test challenges. The methodology will be validated through the design of testchips containing the IP blocks. A rating methodology will be applied during testchips characterization to check the objectives achievement. Exploitation within TAMES-2 will be biased towards marketing the IP blocks embedding advanced DfT solutions, towards the dissemination through international conferences and academic courses, and the submission of the results to standardisation organisations.

Continued below .......

The objective of the TAMES-2 project is to improve the industrial testability of high-resolution analogue to digital interfaces embedded in SoC (System-on-Chip).

The work will respond to three key industrial demands:
- Test cost reduction through minimisation of test time and test development cost;
- Improvements in test coverage and outgoing quality, to address the industrial trend for higher quality product at lower cost;
- development of test reuse concepts and integration of the associated advances in test engineering into the design flow for new interface designs in SoC applications.

TAMES-2 will improve mixed-signal test engineering as it will characterise test solutions at the SoC, architectural and circuit levels, develop reusable test solutions in the mixed signal domain, and push the sate-of-the-art in high-resolution embedded converters.

Work description:
TAMES-2 will be carried out by four partners, two industrial Companies and two academic organisations :
- Alcatel Microelectronics;
- Dolphin Integration;
- Lancaster University and

Each Partner brings to the consortium the necessary and sufficient expertise and knowledge to achieve the objectives of the project. The work to be carried out to achieve the advances proposed in converter test engineering will be driven by the requirements of the industrial users in the consortium.

The main steps of the TAMES-2 project are:
- Study of the requirements for industrial mixed-signal test;
- Definition of suitable innovative DfT Techniques, including BIST at SoC, architectural and circuit level;
- Validation of the objectives of the project through the design of industrial IP blocks, an audio codec and an auto-motive interface, both representing macrocells for use in much larger SoC designs and having complementary test requirements. This design includes specification and architecture of the IP blocks, development of robust schematics for analogue part and RTL model for logical part, implementation of DfT techniques and layout in advanced CMOS processes,- Design and fabrication of testchips including the two IP blocks;
- Characterisation and test of the testchips using on-chip test structures and industrial test equipment together with laboratory test benches for measuring the efficiency of the DfT solutions and the performances of the IP blocks;
- Evaluation of the impact of DfT on the performances of the selected converters;
- Use of the IP blocks by Alcatel Microelectronics through the insertion in its IP library and by Dolphin through inclusion in its IP catalogue;
- Dissemination of results through academic courses and international conferences,- Submission of the result to standardisation organisations (VISA, IEEE).

- Month 12: Description of architectural and structural DfT techniques adapted to the high-resolution converters, specifications of the silicon demonstrators.
- Month 20&30: Characterisation results of the testchips, conclusion on the efficiency of the selected DfT techniques.
- Months 30: Generic recommendations for the test reusability of analogue macrocells, inclusion of the IP blocks in the library of AME, use of the IP blocks through Dolphin, finalisation of dissemination activities.










Organisation: Dolphin Integration
Organisation Type: Other
Address: Avenue du Granier 39
Postcode: 38240
City: Meylan
Country: FRANCE
Other partners









Organisation Name: Alcatel Microelectronics N.V.
Organisation Type: Other
Contact Person: CHICHKOV, Anton
Address: Westerring 15
City: Oudenaarde
Org. Country: BELGIUM
Organisation Name: Consejo Superior de Investigaciones Cientificas
Organisation Type: Research
Contact Person: PEREZ-VERDU, Belen
Department: Instituto de Microelectronica de Sevilla
Address: C/ Serrano, 117
City: Madrid
Org. Country: SPAIN
Postcode: 28006
Organisation Name: The University of Lancaster
Organisation Type: Education
Contact Person: RICHARDSON, Andrew
Department: Departement of Engineering
Address: Bailrigg
City: Lancaster
Region: NORTH
Postcode: LA1 4YW






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